Techniques for Leakage Power Reduction in Nanoscale Circuits: A Survey
نویسنده
چکیده
This report surveys progress in the field of designing low power especially low leakage CMOS circuits in deep submicron era. The leakage mechanism and various recently proposed run time leakage reduction techniques are presented. Two designs from Cadence and Sony respectively, which can represent current industrial application of these techniques, are also illustrated. 1 The work behind this report is carried out as a 13-week special course with associate professor Alberto Nannarelli as supervisor during the autumn semester 2006 at the Department of Informatics and Mathematical Modeling, Technical University of Denmark.
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